1. Technical Field
The present invention relates to floating-point units (FPUs) in general, and, in particular, to a method and apparatus for performing alignment shifting in a floating-point unit.
2. Description of Related Art
Floating-point numbers can be either single precision or double precision as defined by the Institute for Electrical and Electronic Engineers (IEEE) standard. Single precision floating-point numbers have one sign bit, eight exponent bits, and twenty-three mantissa bits with a one implicit bit. Double precision floating-point numbers have one sign bit, eleven exponent bits, and fifty-two mantissa bits with one implicit bit.
The computation logic for floating-point numbers can typically be divided into two types: multiply-add/subtract and distinct multiply and add/subtract. One of the more common methods associated with multiply-add/subtract computation logic is based on three operands A, B and C to provide the operation A*B+C. In order for a floating-point addition/subtraction to take place, the mantissas of two floating-point numbers must be aligned, which is commonly performed by an alignment shifter.
Referring now to the drawings, and specifically to FIG. 1, there is depicted a conventional alignment shifter. As shown, an alignment shifter 100 includes a shift amount calculator 111, a shifter 112, a limiter 113, and a multiplexor 114. Exponent EA of operand A, exponent EB of operand B and exponent EC of operand C enter shift amount calculator 112 and limiter 113 through a line 115, a line 116, and a line 117, respectively.
Shift amount calculations are then performed after shift amount calculator 111 has received exponents EA, EB and EC. The right-shift amount is subsequently communicated to shifter 112 via a line 118. The mantissa MC of operand C from a line 119 is right-shifted by shifter 112 accordingly. After all the shifting have been completed, the data are sent to multiplexor 114 via a line 121. Limiter 13 provides control signals to multiplexor 114 via a line 122 to allow for multiplexor 114 to provide the necessary correction for overflow or underflow.
One problem associated with conventional alignment shifters, such as alignment shifter 100, is under-utilization. Typically, a double-precision alignment shifter can handle either one single precision floating-point number or one double precision floating-point number. In a vectored floating-point implementation, such as single instruction multiple data (SIMD), it would be more efficient for the same double-precision alignment shifter to simultaneous align two single precision floating-point numbers without adding any delay to the critical path.
Consequently, it would be desirable to provide an improved method for performing alignment shifting such that all the resources of a double-precision alignment shifter can be fully utilized.